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ÇÁ·Î¼¼¼ µðÀÚÀο¡¼ Instrcution setÀ» ¾î¶»°Ô ±¸¼ºÇϴ°¡¿Í
Pipelining, cache memory, RISC ÀÇ °í±Þ±â¹ýµéÀ» ¹è¿ì°í, ½Ã½ºÅÛµðÀÚÀο¡¼
I/O ½Ã½ºÅÛ°ú Inteconnection Network ¹× ¼º´ÉÆò°¡ÀÇ ´Ù¾çÇÑ ¹æ¹ýµé¿¡ ´ëÇØ¼
¿¬±¸Çϸç, º´·Ä½Ã½ºÅÛÀÇ ±âº»ÀûÀÎ ³»¿ë°ú ¿¬±¸°úÁ¦¸¦ ÆÄ¾ÇÇÒ¼ö ÀÖµµ·Ï ÇÑ´Ù.
Áß°£°í»ç/Çб⸻°í»ç ±×¸®°í Term Project ¹× Paper summary¸¦
Æ÷ÇÔÇÑ °úÁ¦¸¦ ¼öÇàÇÏ¸é¼ ½ÇÁ¦ÀûÀÎ ´É·ÂÀ» ¹è¾çÇϵµ·Ï ÇÑ´Ù. °Àdz»¿ëÀº
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Performance metrics and cost evaluation of computer systems
(MIPS, MFLOPS, SPEC92, benchmark suits)
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Processor design - alternatives in designing Instruction
Set Architecture
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Pipelining - hazards, instruction-level parallelism, branch
prediction
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Memory hierachy - cache, main memory, virtual memory
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Storage systems - I/O device, I/O performance, RAID, File
system
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Interconnection Network - Multicomputer networks, Network
of workstations, LAN, ATM
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Multiprocessors - Shared memory architecture, distributed
memory architecture, cache coherency, sychronization
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ÇÐÁ¡ ¹èÁ¡
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Midterm Exam 15%
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Final Exam 15%
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Term Project 40%
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Homework 20%
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Class Participation 10%
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°»ç ¼Ò°³
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À¯Âù¼ö Á¶±³¼ö, Á¤º¸°øÇкÎ
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¿¬±¸½Ç : 6¿¬±¸µ¿ 325È£
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ÀüÈ : (042) 860-1389
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Email : cyu@icu.ac.kr,
cyu@hotmail.com
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°Àǽð£ : ¿ù 9:30-11:00, ¼ö 11:00-12:30
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Office hour : ¿ù 15:00-16:00, ¼ö 14:00-15:00
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±³Àç ¼Ò°³
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J. L. Hennessy and D. A. Patterson, Computer Architecture:
A Quantitative Approach, 2nd Edition, Morgan Kaufmann Publishing Co., Menlo
Park, CA.