Course Schedule

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1ÁÖÂ÷ 3/2¿ù *ÀÔÇÐ½Ä (°­ÀǾøÀ½)
3/4¼ö *Overview (ISCA/HPCA, COMPCON)
2ÁÖÂ÷ 3/9¿ù Cost, Performance 1.1-1.5 Paper#1
3/11¼ö Design Principles and RISC 1.6-1.10
3ÁÖÂ÷ 3/16¿ù Instrcution Set Architecture 2.1-2.5 Paper#1
3/18¼ö DLX Summary 2.6-2.11 HW#1 ÇÁ·ÎÁ§Æ®ÆÀ ±¸¼º
4ÁÖÂ÷ 3/23¿ù Pipelining 3.1-3.3
3/25¼ö Data and Control Hazards 3.4-3.5
5ÁÖÂ÷ 3/30¿ù Pipeline Complications 3.6-3.12 HW#1
4/1¼ö Instruction Level Parallelism 4.1
6ÁÖÂ÷ 4/6¿ù Dynamic Scheduling 4.2 Paper#2
4/8¼ö Tomasulo Algorithm 4.2
7ÁÖÂ÷ 4/13¿ù Dynamic Branch Prediction 4.3-4.4
4/15¼ö Studies of ILP 4.5-4.7 Proposal, Phase I 
8ÁÖÂ÷ 4/20¿ù *No Class (Áß°£°í»ç ±â°£) Paper#2 (4/17)
4/22¼ö *Áß°£°í»ç
9ÁÖÂ÷ 4/27¿ù ABCs of Cache 5.1-5.2
4/29¼ö Reducing Cache Misses 5.3 PhaseII (7-8PM: Demo)*
10ÁÖÂ÷ 5/4¿ù Reducing cache Miss Penalty 5.4
5/6¼ö Reducing Hit Time 5.5 HW#2
11ÁÖÂ÷ 5/11¿ù Main Memory 5.6
5/13¼ö Virtual Memory 5.7-5.8
12ÁÖÂ÷ 5/18¿ù Inteconnect Technology 7.1-7.4 HW#2
5/20¼ö Practical Issues and Examples 7.5-7.13 (7-8PM: VLIW)*
13ÁÖÂ÷ 5/25¿ù Multiprocessors 8.1-8.2 PhaseIII Draft, Phase II
5/27¼ö Centralized Shared Memory Multiprocessors 8.3 HW#3
14ÁÖÂ÷ 6/1¿ù Distributed Shared Memory Multiprocessors 8.4
6/3¼ö Synchronization 8.5
15ÁÖÂ÷ 6/8¿ù Memory Consistency 8.6-8.11 HW#3
6/10¼ö Storage Systems 6.1-6.11 Take-home
16ÁÖÂ÷ 6/15¿ù *No class (±â¸»°í»ç ±â°£)
6/17¼ö *±â¸»°í»ç - Oral Presentation Paper, Phase III 
 
  • Class Notes
  • Special Lectures #1
  • Special Lecture #2 (Çкμ¼¹Ì³ª)
  • Special Lecture #3 (Çкμ¼¹Ì³ª)
  • Project presentation #1
  • Project presentation #2