Chapter 2 Instructions: Language of the Computer
    Sections 2.1~3 Operations and Operands
    Sections 2.4~6 Representing Instructions and Logical/Control Flow Operations
    Sections 2.7~9 Procedure, Byte operations, and Addreesing
    Sections 2.10~16 Examples

Chapter 3 Arithmetic for Computers
    Sections 3.1~3 Addition/Subtraction
    Sections 3.4~5 Multiplication/Division
    Section 3.6 Floating Point Numbers
    Appendix B Constructing an ALU

Chapter 4 Assessing and Understanding Performance

Chapter 5 The Processor: Datapath and Control
    Sections 5.1~3 Building a Datapath
    Section 5.4 A Simple Implementation Scheme
    Sections 5.5~7 A Multicycle Implementation, Exception and Multiprogramming
    Appendix B.4 & 5.8 Verilog: Hardware Design Language

Test programs for Project #1
Program 1
Program 2
Program 3
Program 4
Program 5
Program 6
Program 7
Program 8
Program 9
Program 10

Sample Verilog programs for Project #2, Step 1
alu.v
sim_alu.v

Sample Verilog programs for Project #2, Step 2
cpu.v
imem.v
dmem.v
sim.v (modified version, showing register contents, uploaded at 630pm, 042706)

Test dmem/imem files for Project #2
Test program #1 (simple test): test1.asm dmem1.v imem1.v
Test program #2 (branch/j operation): test2.asm dmem2.v imem2.v (corrected version of test2.asm and dmem2.v uploaded at 630pm, 042706)
Test program #3 (memory operation): test3.asm dmem3.v imem3.v
Test program #4 (addi/bne operation): test4.asm dmem4.v imem4.v

Final test dmem/imem files for Project #2
Test program #1 (simple program): t1.asm dm1.v im1.v
Test program #2 (invalid opcode exception): t2.asm dm2.v im2.v
Test program #3 (all ALU operations): t3.asm dm3.v im3.v
Test program #4 (simple add/subtract): t4.asm dm4.v im4.v
Test program #5 (overflow exception): t5.asm dm5.v im5.v
Test program #6 (addi instruction): t6.asm dm6.v im6.v
Test program #7 (bne & addi): t7.asm dm7.v im7.v