Chapter 6 Enhancing Performance with Pipelining

• 6.1 An Overview of Pipelining
• 6.2 A pipelined Datapath
• 6.3 Pipelined Control
• 6.4 Data Hazards and Forwarding
• 6.5 Data Hazards and Stalls
• 6.6 Branch Hazards
• 6.8 Exceptions
• Summary of Chapter 6

• 7.1 Introduction
• 7.2 The Basics of Caches
• 7.3 Cache Performance
• 7.4 Virtual memory

Chapter 9 Multiprocessors and Clusters
 

* Reseacrh Labs in EEC Department, CSU
* Mobile Computing Research Lab (Prof. Chansu Yu)
* Research in MCRL
 

Midterm exam on Oct. 18 (Wed) <- Schedule has been changed!
Final exam during 830-1030AM on Dec. 15 (Fri)

Homework and Due dates

Term Projects