Project description

Project #1: Due on Monday, Sep. 18

• Project #1 description
• Updated on Aug. 30, defining ALUOp (= 11) for LUI
• Updated on Sep. 11, regarding I-type instructions (thanks to Matt)

• Sample Verilog programs for Project #1
• alu_p1.v
• aluctrl_p1.v
• sim_alu.v

• Test programs for Project #1
• sim_alu_1.v (Basic test)
• sim_alu_2.v
• sim_alu_3.v
• sim_alu_4.v
• sim_alu_5.v (Updated on Sep. 13)

• Project #2 description
• Posted on Sep. 18
• Updated on Oct. 12, regarding "j" instruction (thanks to Robert)
• Supplemental figures

Project #3: Due on Wednesday, Nov. 8

• Project #3 description
• Posted on Oct. 22
• Updated on Oct. 24 adding the input/output description
• There will be no test programs posted on the web. You have to provide at least 3 test cases for testing the control circuit (sim_control.v) and another 3 cases for testing the forwarding logic (sim_forwarding.v) when you turn in Project #3.

• Project #4 description
• Posted on Nov. 13
• Forwaring circuit does not need any chnages if you employ two consecutive multiplexers for the second operand of ALU. See the project description for details.
• Make sure that Rs=0 in case of sll/srl instruction.
• Project presentation is scheduled on Dce. 6.
• Revised on Nov. 20 (suggest to print 26 wires)
• Sample Verilog programs for Project #4
• cpu.v
• dmem.v
• imem.v
• sim_cpu.v
• Test dmem/imem files for Project #4
• If you found any problems in the test programs, please email me as soon as you can!!!
• Test program #1 (very basic test): t1.asm dm1.v im1.v
• Test program #2 (all basic instructions): t2.asm dm2.vim2.v
• Test program #3 (beq, lw, sw, j): t3.asm dm3.vim3.v
• Test program #4 (sll, srl, I-type): t4.asm dm4.vim4.v
• Test program #5 (forwarding): t5.asm dm5.vim5.v
• Test program #6 (SignExtImm/ZeroExtImm): t6.asm dm6.vim6.v
• Test program #7 (more forwarding): t7.asm dm7.vim7.v
• im1.v has been corrected, thanks to Dave
• im4.v has been corrected, thanks to Rob
• im1.v ~ im5.v have been corrected (semicolons), thanks to Dave