Midterm exam on Oct. 16 (Thr)
    Coverage: Chapter 6, Appendix B.4 and B.5
    Homework, Quiz
   
Final exam during 4-6PM on Dec. 9 (Tue)

Introduction

• Review: Datapath and Control
• Appendix B.4 & 5.8 Verilog: Hardware Design Language
• Appendix B Constructing an ALU

Chapter 6 Enhancing Performance with Pipelining

• 6.1 An Overview of Pipelining
• 6.2 A Pipelined Datapath
• 6.3 Pipelined Control
• 6.4 Data Hazards and Forwarding
• 6.5 Data Hazards and Stalls
• 6.6 Branch Hazards & 6.8 Exceptions

Chapter 7 Large and Fast: Exploiting Memory Hierarchy

• Review: Cache
• Review: Virtual memory

Chapter 9 Multiprocessors and Clusters