Project #1: Description, alu.v, sim_alu.v
    Test programs for project #1: sim_alu_aluctrl.v
    Test programs for grading: sim_alu2.v, sim_aluctrl2.v, sim_control2.v, sim_three2.v (you need to add or reorder input/out ports)
    Completed design files (examples): p1_alu.v, p1_aluctrl.v, p1_control.v (you may want to use these for project #2)
    References: quick_start_guide, iverilog, iverilog-vpi, vvp, hello.vl, sqrt-virtex
    Helpful links: Bucknell Handbook of Verilog HDL

Project #2 (due Oct. 9): Description
    Sample design files: cpu.v, imem.v, dmem.v, sim.v

Project #3 (due Nov. 6): Description (power point file for your reference)
    Test program #1 (basic test): tt1.asm, mem1.v
    Test program #2 (another basic test): tt2.asm, mem2.v
    Test program #3 (basic instructions): tt3.asm, mem3.v
    Test program #4 (lw, sw): tt4.asm, mem4.v (corrected on 11/17/08)
    Test program #5 (beq, lw, sw, j): tt5.asm, mem5.v (corrected on 11/17/08)
    Test program #6 (beq, bne, j): tt6.asm, mem6.v (corrected on 11/17/08)
    Test program #7 (overflow): tt7.asm, mem7.v

    Assemblers available for generating mem.v files (not tested completely)
        mips1.exe ("mips asm_file" at DOS window, "output filename.vl", and "quit")
            Known bugs: - tab is not processed, bne is not supported, comments in the beginning is not accepted
        mips2.exe (Windows interface, some bugs, just for your reference)

Project #4 (due Dec. 4): Description (See the last page for new information regarding data dependency in conjunction with branch hazard. Taking care of this issue requires a number of considerations as explained in the last page of the Project Description. However, you do not need to change your design because test programs have been modified so that the corresponding cases do not occur. For example, some nop's are added in t5.asm and t6.asm.)
    Test program #1 (forwarding and data hazard detection): t1.asm, m1.v (added on 12/3/08)
    Test program #2 (beq, bne): t2.asm, m2.v (added on 12/3/08)
    Test program #3 (basic instructions): t3.asm, m3.v
    Test program #4 (lw, sw): t4.asm, m4.v (corrected on 11/17/08)
    Test program #5 (beq, lw, sw, j): t5.asm, m5.v (corrected on 11/17/08 12/3/08, and 12/5/08)
    Test program #6 (beq, bne, j): t6.asm, m6.v (corrected on 11/17/08, 12/3/08, and twice on 12/5/08)
    Test program #7 (overflow): t7.asm, m7.v