module sim_alu; // file ¡°sim_alu.v¡± wire [3:0] ALUctl; reg [31:0] A, B; wire [31:0] ALUOut; wire Zero; reg [1:0] ALUOp; reg [5:0] Func; aluctrl ALUC1 (ALUOp, Func, ALUctl); alu ALU1 (ALUctl, A, B, ALUOut, Zero); initial begin //***************** //1st run for A < B //***************** A = 32'd13; //32'b0_1101 B = 32'd20; //32'b1_0100 $display("\n***** 1st Run *****"); $display("A (1st) =", A); $display("B (2nd) =", B); ALUOp = 2'd2; Func = 6'h20; //ALUctl = 4'd2; #1; //This is for waiting until output is settled down. $display(" ADD"); $display("ALUOut = ", ALUOut); $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h22; //ALUctl = 4'd6; #1; $display(" SUB"); $display("ALUOut = ", ALUOut); //should be negative $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h24; //ALUctl = 4'd0; #1; $display(" AND"); $display("ALUOut = ", ALUOut); $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h25; //ALUctl = 4'd1; #1; $display(" OR"); $display("ALUOut = ", ALUOut); //should be 1 (set) $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h2a; //ALUctl = 4'd7; #1; $display(" SLT"); $display("ALUOut = ", ALUOut); $display("Zero = ", Zero); //***************** //2nd run for A = B //***************** A = 32'd20; //32'b1_0100 B = 32'd20; //32'b1_0100 $display("\n***** 2nd Run *****"); $display("A (1st) =", A); $display("B (2nd) =", B); ALUOp = 2'd2; Func = 6'h20; //ALUctl = 4'd2; #1; //This is for waiting until output is settled down. $display(" ADD"); $display("ALUOut = ", ALUOut); $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h22; //ALUctl = 4'd6; #1; $display(" SUB"); $display("ALUOut = ", ALUOut); //should be negative $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h24; //ALUctl = 4'd0; #1; $display(" AND"); $display("ALUOut = ", ALUOut); $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h25; //ALUctl = 4'd1; #1; $display(" OR"); $display("ALUOut = ", ALUOut); //should be 1 (set) $display("Zero = ", Zero); ALUOp = 2'd2; Func = 6'h2a; //ALUctl = 4'd7; #1; $display(" SLT"); $display("ALUOut = ", ALUOut); $display("Zero = ", Zero); $finish; end endmodule