Syllabus and Class schedule
Homework and due dates
Quizzes
Term Projects (revised !!!!!)
    Test program: alu.vhdl, sim_alu.vhdl (VHDL)
    Test program: alu.v, sim_alu.v (Verolog)
    Helpful links (Verilog): Bucknell Handbook of Verilog HDL
    Test program for grading: grading_sim_alu.vhdl, grading_sim_aluctrl.vhdl, grading_sim_control2.vhdl, grading_sim_three.vhdl
    * Working project #1 for developing later projects: alu.vhd, alu_1bit.vhd, adder_1bit.vhd, aluctrl.vhd, control.vhd, mux2.vhd, mux4.vhd

Project #2 (Due: Oct. 27)
    Test framework: cpu.vhdl, test.vhdl, sim.vhdl, UTILS.vhdl, SEE THIS
    Yet another (better) test framework: testMem.vhdl, sim2.vhdl, UTILS2.vhdl, registers.vhdl, BE SURE TO READ THIS COMMENTS
    Test program for grading: t1.vhdl (t1.v), t2.vhdl, t3.vhdl, t4.vhdl, t6.vhdl
    Test framework in Verilog: cpu.v, imem.v, dmem.v, sim.v (Verilog)
    Make sure that your design uses the same module names (cpu, imem and dmem) and the same number/size/order of ports in each module. For example, imem module has two ports, 32-bit address and 32-bit data, in that order.

Project #3 (Due: Dec. 8)
  Here are the test programs for Project #3. For your reference, the corresponding assembly files are also posted.
  For the basic test, the project is not assumed to implement forwarding, hazard detection, branch hazard, and exception. Therefore, for example, three "nop"s are inserted whenever there is a data hazard. (In fact, two nop's are sufficient if writing to, for example, $5 (1st half of the cycle) and reading from $5 are allowed during the same cycle.)
    t31.asm = mem31.vhdl - basic test (with 3 nops)
    t32.asm = mem32.vhdl - basic test (with 2 nops)
    t33.asm = mem33.vhdl - instruction test
    t34.asm = mem34.vhdl - lw/sw
    t35.asm = mem35.vhdl - loop test (beq/j) (mem35.vhdl has been corrected)
    t36.asm = mem36.vhdl - jumps (j)
  There's another set of test programs that test advanced features like forwarding, hazard detection, branch hazard, and exception.
    t41.asm = mem41.vhdl - forwarding/hazard test
    t42.asm = mem42.vhdl - branch hazard
    t43.asm = mem43.vhdl - more forwarding test
    t44.asm = mem44.vhdl - more hazard test
    t45.asm = mem45.vhdl - more branch test with loops
    t46.asm = mem46.vhdl - more jump test
    t47.asm = mem47.vhdl - overflow exception
  When you turn in your project, be sure to clearly mention in a separate file, named readme, that your project works ok (in terms of the number of cycles and register contents) with each of the thirteen test programs. I do not want to take points off for the test cases you tested ok but do not work ok in my side. Also, you must be ready to respond to my emails regarding your design.

Chapter 2 Instructions: Language of the Computer
    Sections 2.1~3 Operations and Operands
    Sections 2.4~7 Representing Instructions and Logical/Control Flow Operations
    Sections 2.8~10 Procedure, Byte operations, and Addressing

Chapter 3 Arithmetic for Computers
    Sections 3.3~5 Arithmetic Operations
    Appendix C.5 Constructing an ALU

Chapter 4 The Processor: Datapath and Control
    Sections 4.1~3 Building a Datapath
    Section 4.4 A Simple Implementation Scheme
    Section 4.5 An Overview of Pipelining
    Section 4.6 A Pipelined Datapath
    Section 4.6 Pipeline Control
    Section 4.7 Data Hazards, Forwarding and Stalls
    Section 4.8~9 Control Hazards & Exceptions

Chapter 5 Large and Fast: Exploiting Memory Hierarchy
    Section 5.1 Memory Hierarchy
    Section 5.2 Basics of Caches
    Section 5.3 Cache Performance
    Section 5.4 Virtual Memory

Chapter 6 Storage and Other I/O Topics
    Section 6.1~2 & 6.7~8 Storage and I/O

Chapter 7 Multicores, Multiprocessors, and Clusters
    Section 7.1~2 Multiprocessors