목차
PPT 슬라이드
Outline
Why RISC processor optimization ?
Cray T3E Hardware Overview
Microprocessor (DEC alpha 21164)
On-chip Memory Hierarchy
Support Circuitry
How to develop an optimal code
Programming Environment on Cray T3E
Apprentice
PAT (Performance Analysis Tool)
Time Checking Routines
Compile Options (FORTRAN)
Functional Unit Optimizations
Cache Optimizations
Cache Optimizations
Stream Buffer Optimizations
Stream Buffer Optimizations
Stream Buffer Optimizations
E-register Optimizations
E-register Optimizations
Case Study: NAS Benchmark Kernals
Concluding Remarks
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작성한 사람: 지원실
전자 우편: cyu@icu.ac.kr
홈 페이지: http://vega.icu.ac.kr/~cyu/courses/prog99/99prog.html
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