FPGA Prototyping by Verilog Examples: Spartan-3 Version

A new version of this text, FPGA Prototyping by SystemVerilog, is available.

• SystemVerilog vs. Verilog in RTL design

This web page provides relevant materials for the FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version t text

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Sample materials

• Preface and Table of Contents
• Sample chapter on UART
  (copyrighted by John, Wiley & Sons and cannot be printed or reposted on the web)

Source codes

• source code zip file

FAQ (last updated 06/24/2008)

• pdf file

Instructional materials

The files are for the course instructors only and are password protected. Please send Dr. Chu an e-mail with a web link that can verify your status. 

• Figures and tables