RTL Hardware Design Using VHDL
This web page provides relevant materials for the RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Salability text.
Reviews
Sample materials
- Preface and Table of Contents
- Sample chapter on FSM
(copyrighted by John, Wiley & Sons and cannot be printed or reposted on the web)
Source codes
Errata (last updated 12/01/2006)
Instructional materials
The files are for the course instructors only and are password protected. Please send Dr. Chu an e-mail with a web link that can verify your status.