{"id":253,"date":"2023-02-15T20:37:53","date_gmt":"2023-02-15T20:37:53","guid":{"rendered":"https:\/\/academic.csuohio.edu\/chu-pong\/?page_id=253"},"modified":"2023-02-15T20:43:10","modified_gmt":"2023-02-15T20:43:10","slug":"fpga-verilog","status":"publish","type":"page","link":"https:\/\/academic.csuohio.edu\/chu-pong\/fpga-verilog\/","title":{"rendered":"FPGA Verilog"},"content":{"rendered":"\n<h1 class=\"wp-block-heading\"><strong><em>FPGA Prototyping by Verilog Examples: Spartan-3 Version<\/em><\/strong><\/h1>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog0.jpg\" alt=\"\" class=\"wp-image-148\" width=\"160\" height=\"231\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog0.jpg 547w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog0-208x300.jpg 208w\" sizes=\"auto, (max-width: 160px) 100vw, 160px\" \/><\/figure>\n\n\n\n<p>A new version of this text, <em><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/sv-mcs-book\/\" data-type=\"page\" data-id=\"123\">FPGA Prototyping by SystemVerilog<\/a><\/em>, is available.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/SystemVerilog-vs-Verilog-in-RTL-design.pdf\" data-type=\"attachment\" data-id=\"122\" target=\"_blank\" rel=\"noopener\">SystemVerilog vs. Verilog in RTL design<\/a><\/li>\n<\/ul>\n\n\n\n<p>This web page provides relevant materials for the&nbsp;<em>FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version<\/em>&nbsp;t<em>&nbsp;<\/em>text<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Reviews at <a href=\"https:\/\/www.amazon.com\/FPGA-Prototyping-Verilog-Examples-Spartan-3\/dp\/0470185325\" target=\"_blank\" rel=\"noopener\">Amazon <\/a><\/h3>\n\n\n\n<h3 class=\"wp-block-heading\">Sample materials<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/fpga_vlog_preface.pdf\" data-type=\"attachment\" data-id=\"255\">Preface<\/a> and <a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/fpga_vlog_toc.pdf\" data-type=\"attachment\" data-id=\"258\" target=\"_blank\" rel=\"noopener\">Table of Contents<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/fpga_vlog_sample_chapter.pdf\" data-type=\"attachment\" data-id=\"256\" target=\"_blank\" rel=\"noopener\">Sample chapter&nbsp;on UART<\/a> <br>(copyrighted by John, Wiley &amp; Sons and cannot be printed or reposted on the web)<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Source codes<\/strong><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/fpga_vlog_src.zip\" data-type=\"attachment\" data-id=\"257\" target=\"_blank\" rel=\"noopener\">source code zip file<\/a><\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><strong><strong>FAQ (last updated 06\/24\/2008)<\/strong><\/strong><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/fpga_vlog_faq.pdf\" data-type=\"attachment\" data-id=\"259\">pdf file<\/a><\/li>\n<\/ul>\n\n\n\n<div style=\"height:18px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Instructional materials<\/strong><\/h3>\n\n\n\n<p>The files are for the course instructors only and are password protected.&nbsp;Please send Dr. Chu an e-mail with a web link that can verify your status.&nbsp;<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/drive.google.com\/file\/d\/1fXnHFjQ7RL4snMI9jiQGzutfRkHOT20x\/view?usp=sharing\">Figures and tables <\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>FPGA Prototyping by Verilog Examples: Spartan-3 Version A new version of this text, FPGA Prototyping by SystemVerilog, is available. This web page provides relevant materials for the&nbsp;FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version&nbsp;t&nbsp;text Reviews at Amazon Sample materials Source codes FAQ (last updated 06\/24\/2008) Instructional materials The files are for the course instructors only&mldr;<\/p>\n","protected":false},"author":39,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_relevanssi_hide_post":"","_relevanssi_hide_content":"","_relevanssi_pin_for_all":"","_relevanssi_pin_keywords":"","_relevanssi_unpin_keywords":"","_relevanssi_related_keywords":"","_relevanssi_related_include_ids":"","_relevanssi_related_exclude_ids":"","_relevanssi_related_no_append":"","_relevanssi_related_not_related":"","_relevanssi_related_posts":"","_relevanssi_noindex_reason":"","footnotes":""},"class_list":["post-253","page","type-page","status-publish","hentry"],"featured_image_src":null,"_links":{"self":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages\/253","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/users\/39"}],"replies":[{"embeddable":true,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/comments?post=253"}],"version-history":[{"count":7,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages\/253\/revisions"}],"predecessor-version":[{"id":265,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages\/253\/revisions\/265"}],"wp:attachment":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/media?parent=253"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}