{"id":71,"date":"2023-02-13T14:29:31","date_gmt":"2023-02-13T14:29:31","guid":{"rendered":"https:\/\/academic.csuohio.edu\/chu-pong\/?page_id=71"},"modified":"2023-02-17T04:08:14","modified_gmt":"2023-02-17T04:08:14","slug":"dr-chus-books","status":"publish","type":"page","link":"https:\/\/academic.csuohio.edu\/chu-pong\/dr-chus-books\/","title":{"rendered":"Dr. Chu&#8217;s books"},"content":{"rendered":"\n<h1 class=\"wp-block-heading\">Dr. Chu&#8217;s books<\/h1>\n\n\n\n<h2 class=\"wp-block-heading\">Book reviews at <a rel=\"noopener\" href=\"https:\/\/www.amazon.com\/stores\/Pong-P.-Chu\/author\/B001ITRMEY\" target=\"_blank\">Amazon <\/a>.  <\/h2>\n\n\n\n<h2 class=\"wp-block-heading\">Book companion materials (follow the link):<\/h2>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl2.jpg\" alt=\"\" class=\"wp-image-89\" width=\"113\" height=\"169\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl2.jpg 230w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl2-199x300.jpg 199w\" sizes=\"auto, (max-width: 113px) 100vw, 113px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/fpga-vhdl-soc-book\/\" data-type=\"page\" data-id=\"220\">FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC Edition<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:16px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_sv.jpg\" alt=\"\" class=\"wp-image-72\" width=\"116\" height=\"165\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_sv.jpg 351w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_sv-211x300.jpg 211w\" sizes=\"auto, (max-width: 116px) 100vw, 116px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/sv-mcs-book\/\" data-type=\"page\" data-id=\"123\">FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:16px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl0.jpg\" alt=\"\" class=\"wp-image-144\" width=\"120\" height=\"181\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl0.jpg 228w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl0-198x300.jpg 198w\" sizes=\"auto, (max-width: 120px) 100vw, 120px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/fpga-vhdl\/\" data-type=\"page\" data-id=\"270\">FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:19px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog0.jpg\" alt=\"\" class=\"wp-image-148\" width=\"118\" height=\"170\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog0.jpg 547w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog0-208x300.jpg 208w\" sizes=\"auto, (max-width: 118px) 100vw, 118px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/fpga-verilog\/\" data-type=\"page\" data-id=\"253\" target=\"_blank\" rel=\"noopener\">FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:25px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl1.jpg\" alt=\"\" class=\"wp-image-152\" width=\"117\" height=\"176\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl1.jpg 230w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vhdl1-199x300.jpg 199w\" sizes=\"auto, (max-width: 117px) 100vw, 117px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/sopc-vhdl\/\" data-type=\"page\" data-id=\"295\" target=\"_blank\" rel=\"noopener\">Embedded SoPC Design with Nios II Processor and VHDL Examples<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:25px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog1.jpg\" alt=\"\" class=\"wp-image-146\" width=\"117\" height=\"176\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog1.jpg 331w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_vlog1-199x300.jpg 199w\" sizes=\"auto, (max-width: 117px) 100vw, 117px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/sopc-verilog\/\" data-type=\"page\" data-id=\"307\">Embedded SoPC Design with Nios II Processor and Verilog Examples<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:25px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_rtl.jpg\" alt=\"\" class=\"wp-image-147\" width=\"117\" height=\"188\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_rtl.jpg 311w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_rtl-187x300.jpg 187w\" sizes=\"auto, (max-width: 117px) 100vw, 117px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/academic.csuohio.edu\/chu-pong\/rtl-vhdl\/\" data-type=\"page\" data-id=\"281\">RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability&nbsp;<\/a><\/figcaption><\/figure>\n\n\n\n<div style=\"height:8px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<div style=\"height:25px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_ch2.jpg\" alt=\"\" class=\"wp-image-153\" width=\"125\" height=\"186\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_ch2.jpg 335w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_ch2-201x300.jpg 201w\" sizes=\"auto, (max-width: 125px) 100vw, 125px\" \/><figcaption class=\"wp-element-caption\">\u57fa\u4e8eNios II\u7684\u5d4c\u5165\u5f0fSoPC\u7cfb\u7edf\u8bbe\u8ba1\u4e0eVerilog\u5f00\u53d1\u5b9e\u4f8b&nbsp;&nbsp;<a href=\"http:\/\/30www.phei.com.cn\/module\/goods\/wssd_content.jsp?bookid=42797\"> <\/a><br><em>Chinese translation of &#8220;Embedded SoPC Design with Nios II Processor and Verilog Examples&#8221;<\/em><\/figcaption><\/figure>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_ch1.jpg\" alt=\"\" class=\"wp-image-108\" width=\"118\" height=\"166\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_ch1.jpg 569w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_ch1-213x300.jpg 213w\" sizes=\"auto, (max-width: 118px) 100vw, 118px\" \/><figcaption class=\"wp-element-caption\">\u7528Verilog\u8bbe\u8ba1FPGA\u6837\u673a\u5b9e\u4f8b\u89e3\u6790<br><em>Chinese translation of <\/em>&#8220;<em>FPGA Prototyping with Verilog Examples<\/em>&#8220;<\/figcaption><\/figure>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_kr.jpg\" alt=\"\" class=\"wp-image-110\" width=\"118\" height=\"164\" srcset=\"https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_kr.jpg 500w, https:\/\/academic.csuohio.edu\/chu-pong\/wp-content\/uploads\/sites\/64\/2023\/02\/cover_kr-217x300.jpg 217w\" sizes=\"auto, (max-width: 118px) 100vw, 118px\" \/><figcaption class=\"wp-element-caption\">&nbsp;<strong>Verilog \uc608\uc81c\ub85c \ubc30\uc6b0\ub294 FPGA \ud504\ub85c\ud1a0\ud0c0\uc774\ud551<\/strong><br><em>Korean translation of <\/em>&#8220;<em>FPGA Prototyping with Verilog Examples<\/em>&#8220;<\/figcaption><\/figure>\n\n\n\n<div style=\"height:100px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Dr. Chu&#8217;s books Book reviews at Amazon . Book companion materials (follow the link):<\/p>\n","protected":false},"author":39,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_relevanssi_hide_post":"","_relevanssi_hide_content":"","_relevanssi_pin_for_all":"","_relevanssi_pin_keywords":"","_relevanssi_unpin_keywords":"","_relevanssi_related_keywords":"","_relevanssi_related_include_ids":"","_relevanssi_related_exclude_ids":"","_relevanssi_related_no_append":"","_relevanssi_related_not_related":"","_relevanssi_related_posts":"","_relevanssi_noindex_reason":"","footnotes":""},"class_list":["post-71","page","type-page","status-publish","hentry"],"featured_image_src":null,"_links":{"self":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages\/71","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/users\/39"}],"replies":[{"embeddable":true,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/comments?post=71"}],"version-history":[{"count":60,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages\/71\/revisions"}],"predecessor-version":[{"id":313,"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/pages\/71\/revisions\/313"}],"wp:attachment":[{"href":"https:\/\/academic.csuohio.edu\/chu-pong\/wp-json\/wp\/v2\/media?parent=71"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}