FPGA Prototyping by SystemVerilog Examples
This web page provides relevant materials for the FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC text
SystemVerilog vs. Verilog in RTL design
General
- Color figures (supplement to the printed version)
- Updated FPro System Development Tutorial
Source codes
- read_me file: readme_source_code.pdf
- source file: fpga_mcs_sv_src.zip (last updated 05/19/2018)
Basys 3 supplement materials
- read_me file: readme_basys3_adoption.pdf
- source file: basys3_supplement_src.zip (last updated 12/05/2017)
Arty A7 supplement materials
- read_me file: readme_arty_a7_adoption.pdf
- source file: arty_supplement_src.zip (last updated 12/05/2017)
Project files w/ Nexys 4 DDR board (in Vivado v2017.2)
Project files w/ Basys 3 board (in Vivado v2017.2)
Project files w/ Arty A7 board (in Vivado v2017.2)
Instructional materials
The files are for the course instructors only and are password protected. Please send Dr. Chu an e-mail with a web link that can verify your status.